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author | orwell96 <orwell@bleipb.de> | 2018-07-21 16:31:00 +0200 |
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committer | orwell96 <orwell@bleipb.de> | 2018-07-21 16:31:00 +0200 |
commit | c34794e8a1a28826a7e8443b46fa76e0de238978 (patch) | |
tree | c4b424764498f14dad06640607e557280f715c7c /advtrains_interlocking/database.lua | |
parent | 5fc5eb9c2abd1cc30277cfda953b4696274ecd31 (diff) | |
download | advtrains-c34794e8a1a28826a7e8443b46fa76e0de238978.tar.gz advtrains-c34794e8a1a28826a7e8443b46fa76e0de238978.tar.bz2 advtrains-c34794e8a1a28826a7e8443b46fa76e0de238978.zip |
Implement routesetting
Missing things: signal aspect updating, waiting routes handling, management /info tool
Diffstat (limited to 'advtrains_interlocking/database.lua')
-rw-r--r-- | advtrains_interlocking/database.lua | 30 |
1 files changed, 26 insertions, 4 deletions
diff --git a/advtrains_interlocking/database.lua b/advtrains_interlocking/database.lua index 6d86e39..c19f516 100644 --- a/advtrains_interlocking/database.lua +++ b/advtrains_interlocking/database.lua @@ -64,6 +64,7 @@ Whenever train leaves a TC -> Clearing any routes set from this TC outward recursively - see "Reversing problem" Whenever train enters a TC -> Clear route status from the just entered TC +Note that this prohibits by design that the train clears the route ahead of it. == Reversing Problem == Encountered at the Royston simulation in SimSig. It is solved there by imposing a time limit on the set route. Call-on routes can somehow be set anyway. Imagine this setup: (T=Train, R=Route, >=in_dir TCB) @@ -108,10 +109,18 @@ function ildb.load(data) if data.signalass then signal_assignments = data.signalass end + if data.rs_locks then + advtrains.interlocking.route.rte_locks = data.rs_locks + end end function ildb.save() - return {tcbs = track_circuit_breaks, ts=track_sections, signalass = signal_assignments} + return { + tcbs = track_circuit_breaks, + ts=track_sections, + signalass = signal_assignments, + rs_locks = advtrains.interlocking.route.rte_locks, + } end -- @@ -144,9 +153,21 @@ Track section name = "Some human-readable name" tc_breaks = { <signal specifier>,... } -- Bounding TC's (signal specifiers) -- Can be direct ends (auto-detected), conflicting routes or TCBs that are too far away from each other - route = {origin = <signal>, from_tcb = <index>} + route = { + origin = <signal>, -- route origin + entry = <sigd>, -- supposed train entry point + rsn = <string>, + first = <bool> + } + route_post = { + locks = {[n] = <pts>} + next = <sigd> + } -- Set whenever a route has been set through this TC. It saves the origin tcb id and side - -- (=the origin signal). index is the TCB of the route origin + -- (=the origin signal). rsn is some description to be shown to the user + -- first says whether to clear the routesetting status from the origin signal. + -- locks contains the positions where locks are held by this ts. + -- 'route' is cleared when train enters the section, while 'route_post' cleared when train leaves section. trains = {<id>, ...} -- Set whenever a train (or more) reside in this TC } @@ -379,10 +400,11 @@ function ildb.remove_from_interlocking(sigd) end function ildb.remove_tcb(pos) + local pts = advtrains.roundfloorpts(pos) + if not track_circuit_breaks[pts] then return end for connid=1,2 do ildb.remove_from_interlocking({p=pos, s=connid}) end - local pts = advtrains.roundfloorpts(pos) track_circuit_breaks[pts] = nil end |